Intel FPGA Technical Training

   
  
 
Fundamentals Part 1

Course Name          : Introduction to Verilog HDL
Course Duration      : 1 Day
Price/Availability     : Contact Us
Course Description :
This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of the Verilog module, data types, operators and assignment statements needed to begin creating your own designs,  using both behavioral and structural approaches. In the hands-on laboratory sessions, you will get to practice the knowledge you have gained by writing simple but practical designs. You will check your designs by compiling in the Quartus® II software version 10.1 and simulating in the ModelSim®-Altera® tool.
  
Course Name          : Introduction to VHDL
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
This one-day class is a general introduction to the VHDL language and its use in programmable logic design, covering constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of VHDL so that you can begin creating your own designs, using both behavioral and structural approaches. In the hands-on laboratory sessions, you will get to practice the knowledge you have gained by writing simple but practical designs. You will check your designs by compiling in the Quartus® II  software v. 13.1 and simulating in the ModelSim®-Altera® tool.
 
Course Name          : The Quartus Prime Software : Foundation
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
You will learn how to use the Quartus® Prime Pro Edition software to develop an FPGA design from initial design to device programming. You will create a new project, input new or existing design files, and compile your project. You’ll learn how to search for compilation information, use settings and assignments to adjust the results of compilation, and manage I/O-related
assignments using the Pin Planner and the BluePrint Platform Designer. You will also learn about device programming files and how to program an FPGA device on your board. You will learn techniques to help you plan your design. You will employ Quartus Prime features that can help you achieve design goals faster. You will also learn how to plan and manage I/O assignments for your target device.
 
 
Fundamentals Part 2

Course Name          : Advanced Verilog HDL Design Techniques
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
You will learn efficient coding techniques for writing synthesizable Verilog for programmable logic devices (FPGAs and CPLDs). While the concepts presented mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices and synthesis tools as well. You will gain experience in behavioral and structural coding while learning how to effectively write common logic functions including registers, memory, and arithmetic functions. You will learn how to use Verilog constructs to parameterize your design, increasing their flexibility and reusability. You will be introduced to testbenches and Verilog constructs used when building them. The exercises will use the Quartus II software to synthesize Verilog code and the ModelSim®-Altera tool for simulation.
 
Course Name          : Advanced VHDL Design Techniques
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
You will learn & practice efficient coding techniques for writing synthesizable VHDL for programmable logic devices (FPGAs & CPLDs). While the concepts presented will mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices & synthesis tools. You will gain experience writing behavioral & structural code & learn to effectively code common logic functions including registers, memory, & arithmetic functions.
You will use VHDL constructs to parameterize your designs to increase their flexibility & reusability. You will also be introduced to testbenches, VHDL constructs used to build them, & common ways to write them. The exercises will use the Quartus II software version to process VHDL code & ModelSim®-Altera software for simulation.
 
Course Name          : Quartus Software Design Series : Timing Analysis
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
You will learn how to constrain and analyze a design for timing using the TimeQuest timing analyzer in the Quartus® software v. 16.0. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.

Course Name          : Introduction to Qsys System Integration Tool
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
This class will teach you how to quickly build designs for Altera® FPGAs using Altera’s Qsys system-level integration tool. You will become proficient with Qsys and expand your knowledge of the Quartus® II FPGA design software v. 14.0. You will learn how to quickly integrate IP and custom logic into a system. Since Qsys makes design reuse easy through standard interfaces, we will examine the Altera Avalon-Memory Mapped and Streaming interfaces as well as introduce the AMBA™ AXI® interface standard from ARM®.  The class provides a significant hands-on component, where you will gain exposure to tool usage as well as system and custom HDL component design.

Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
Debugging and optimizing a large FPGA design can be difficult and time consuming. Every change made to fix a problem or to help close timing requires the design to be completely recompiled. Not only can this take a long time, but the performance of untouched parts of the design can be affected. Integrating the work of different members on a team into a single design only adds to the complexity. In this class, you will learn how to use the incremental compilation feature and LogicLock regions in the Quartus® II software to help reduce compile times, preserve performance, and close timing. You’ll see how the tools in the Quartus II software make it easy to follow an incremental design flow that will help you finish your design cycles sooner.
 
 
 
Advanced Hardware Track

Course Name          : Advanced Timing Analysis with TimeQuest
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
Using the Quartus® II software version 15.0 and building upon your basic understanding of creating Synopsys Design Constraint (SDC) timing constraints, this class will guide you towards understanding, in more depth, timing exceptions. You will learn how to apply timing constraints to more advanced interfaces such as source synchronous single-data rate (SDR), double-data rate (DDR) and LVDS, as well as clock and data feedback systems. You will discover how to write timing constraints directly into an SDC file rather than using the GUI and then enhance the constraint file using TCL constructs. You will also perform timing analysis through the use of TCL scripts.
 
Course Name          : Advanced Qsys System Integration Tool Methodologies
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
In this class, you will learn advanced features of Altera’s Qsys system level integration tool in the Quartus® Prime design software v. 15.1. You will learn how to simulate Qsys systems in ModelSim-Altera Edition using Avalon bus functional simulation models (BFMs), exercise, monitor, and debug systems with System Console, and build hierarchical Qsys systems. You will also learn how to further customize your components through Tcl scripting. Optimization techniques for improving performance and closing timing are also discussed. The class provides a significant hands-on component, where you will gain exposure to tool usage as well
as system design.

Course Name          : Timing Closure with the Quartus II Software
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
One of the greatest and most frustrating FPGA design challenges is closing timing. It is common to find, after performing a timing analysis on an FPGA design, that one or more timing reports show a timing failure. How can this be corrected? The answer is not always obvious. This class teaches techniques used by Design Specialists to close timing on designs that "push the envelope” of performance. Examples include thoroughly analyzing the design for timing failures, adjusting settings and assignments according to tool recommendations, selecting correct clock resources and writing HDL code for optimal performance. For Stratix 10, consider these courses instead: Performance Optimization with Stratix 10 HyperFlex Architecture, Advanced Optimization with Stratix 10 HyperFlex Architecture 
 
Course Name          : Performance Optimization with Stratix 10 HyperFlex Architecture
Course Duration      : 1 Day
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Course Description :
In the Performance Optimization with Stratix® 10 HyperFlex™ Architecture course, you will learn Intel® Quartus® Prime Pro software features and some basic design techniques that will enable your designs to take advantage of the Stratix 10 HyperFlex architecture. In the training, you will learn two steps to improving your performance with the HyperFlex architecture, namely Hyper-Retiming and Hyper-Pipelining, with each step allowing you to move your design up the
performance curve.
Note: While the focus of this course is the Stratix 10 device family, many of the techniques you will learn can be used to improve performance in other device architectures.
 
Course Name          : Advanced Optimization with Stratix 10 HyperFlex Architecure
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
Are you targeting a Stratix® 10 device and want to learn how your design can reach the maximum core performance?
In this course, you'll learn design techniques to enable you to unleash the full potential of the Stratix 10 HyperFlex™ architecture using Hyper-Optimization. You will learn how to identify logic structures that are limiting retiming and thus design performance. You will then learn how to modify your coding style and logic structures and, as a result, allow your design to achieve clock rates of up to 2 times compared to a non-optimized design, without changing overall
design functionality.
Note: While the focus of this course is the Stratix 10 device family, many techniques you will learn can be used to improve performance in other device architectures 
 
Course Name          : Partial Reconfiguration with Arria 10 FPGAs
Course Duration      : 1 Day
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Course Description :
One advantage of an FPGA is the ability to change its function through reconfiguration. This normally replaces the entire FPGA design. What if you could reconfigure just part of the overall design, replacing blocks with different functionality while the main design is still running? In this class, you'll learn how to implement Partial Reconfiguration (PR) in an Intel® FPGA. Focusing on 20 nm Arria 10 devices, you'll know how to change the functionality of a portion of the device, while the rest operates without interruption. Explore the benefits and limitations of PR, understand design guidelines, and learn the steps to enable this feature. Through lab exercises,
you will prepare a design for PR using the Quartus® Prime Pro software, complete the design, and test the feature on a board.
 
 
IO Interfaces Track

Course Name          : Building Interfaces with Arria 10 High-Speed Transceivers
Course Duration      : 1 Day
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Course Description :
In this course, you will learn how you can build high-speed, gigabit interfaces using the 20-nm embedded transceivers found in Arria® 10 FPGA families. You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols. You will learn how to optimize and debug both the digital and analog sections of your transceiver design. You will gain an understanding of the transceiver reconfiguration interface that you can use dynamically adjust transceiver settings to add flexibility to your transceiver design. Lastly, you will learn how to create application and control logic that effectively manages Arria 10 transceiver resources.
 
Course Name          : Creating PCI Express Links with FPGAs
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
Are you beginning or working on a design that uses one or more PCI Express® interfaces? Do you have questions regarding bringing up your FPGA’s PCIe® link? Then this course should be of interest to you!
We'll start with a high-level overview of the PCI Express protocol and from there you'll learn the design flow to target the Hard IP for PCI Express blocks found in Cyclone® V, Arria® V, Stratix® V and Arria 10 devices, particularly when using the Qsys system design tool. You'll see how to debug and test your PCIe links, both through simulation and in-system. You'll discover advanced device features to add more flexibility and capability to your PCI Express-based design. By the end of the day, you'll feel comfortable getting your own device’s PCIe
link up and running.
 
 
Digital Signal Processing Track

Course Name          : Designing with DSP Builder Advanced Blockset
Course Duration      : 1 Day
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Course Description :
Learn the timing-driven Simulink® design flow to implement high-speed DSP designs. This course focuses on implementing DSP algorithms using the advanced blockset capability of DSP Builder—an interface between Quartus® II software & MATLAB® and Simulink tools from The MathWorks. You'll analyze & design your DSP algorithm using the DSP Builder advanced blockset in MATLAB & Simulink. You'll explore architecture & performance tradeoffs with system-level constraints. Also you'll verify functionality & performance of generated hardware in the Quartus II software. Finally, you'll speed design time by incorporating ready made ModelIP cores in your design 
 
 
Embedded Hardware Track

Course Name          : Desiging with an ARM-based SoC
Course Duration      : 1 Day
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Course Description :
Learn to design for a system containing the ARM® Cortex-A9 Hard Processor System (HPS) on Cyclone® V, Arria® V, & Arria 10 SoCs. This course focuses on the hardware aspects of designing the SoC system & includes hands-on labs to get you up & running quickly. Learn to add & configure the processor component into a Qsys system. You'll perform debug of the hardware system using standard debug tools such as SignalTap II logic analyzer & System Console. We'll discuss hardware to software files handoff that simplifies aspects of software development. You'll perform low-level debug of the FPGA interacting with the software debugger. We'll also discuss various ways the FPGA & HPS components can be loaded & booted. At completion, you'll be able to use the SoC device in your own design.
 
 
Software Development Track

Course Name          : Developing Software for an ARM-based SoC
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
This course is for firmware and low-level software engineers and is intended to teach you about software bring-up and development on the embedded ARM® Cortex-A9 hard processor system (HPS) in an SoC. The course isn’t intended to teach you software application or driver development, but rather concentrates on the unique aspects of the embedded HPS software flow in an Altera® SoC. You’ll learn everything needed to get started developing software for
the HPS system, where to go for additional help, as well as how to use the Altera edition of the ARM DS-5 software development tool to debug your software. 
 
Course Name          : OpenCL on FPGA for Parallel Software Programmers
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
This course will teach you how to accelerate algorithms on FPGAs using the OpenCL™
framework. In this class, we will cover the FPGA technologies that make it an ideal coprocessor to boost performance. We will discuss how to use the Intel® FPGA SDK for OpenCL to synthesize OpenCL constructs into custom logic to easily leverage the advantages of FPGA accelerated computing. We will go over the constructs of the OpenCL standard & the Intel FPGA flow that automatically converts kernel C code into hardware that interacts with the host. In the hands-on labs, you’ll write OpenCL programs targeting FPGAs 
 
Course Name          : Introduction to OpenCL for Intel FPGAs
Course Duration      : 1 Day
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Course Description :
OpenCL™ is a standard for writing parallel programs for heterogeneous systems. With the Intel® FPGA SDK for OpenCL, OpenCL constructs are synthesized into custom logic for optimal acceleration on FPGA devices. This course introduces the basic concepts of parallel computing. It covers the constructs of the OpenCL standard & the Intel FPGA flow that automatically converts kernel C code into hardware that interacts with the host. In hands-on labs, you’ll write programs to run in emulation mode as well as on an FPGA board 

Course Name          : Optimizing OpenCL for Intel FPGAs
Course Duration      : 2 Day
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Course Description :
This course covers the optimization techniques needed to implement a high performance OpenCL™ solution on FPGAs. We will use the various debug and analysis tools availablein the Intel® FPGA SDK for OpenCL to boost the performance of your OpenCL kernels. The first half of the course focuses on the optimization of single work-item kernels and the utilization of Intel FPGA channels and OpenCL pipes. The second half of the course focuses on the optimization of ND range kernels and the effective utilization of various memory systems implemented by the Intel FPGA kernel compiler. Throughout the course we will discuss good OpenCL coding design practices for FPGAs and use Intel FPGA SDK for OpenCL features to improve OpenCL
performance on FPGAs 
 
Course Name          : Developing a Custom OpenCL BSP
Course Duration      : 1 Day
Price/Availability     : Contact us
Course Description :
The OpenCL™ model is based on heterogeneous accelerator devices and an FPGA is one of the most scalable & flexible devices available. Since an FPGA is not limited to the traditional host & accelerator communication interfaces, it also allows developers flexibility with ingress & egress of data. To leverage this flexibility requires building a custom Board Support Package
for your custom board. We provide several reference platforms to get started that contain hardware & software layers that can be modified based on board requirements. This training will cover the steps to create a custom BSP compatible with the Intel® FPGA SDK for OpenCL & you'll learn to generate hardware & software deliverables to convert the Arria® 10 reference platform BSP to an Arria 10 custom platform BSP.